Solid state imaging apparatus

ABSTRACT

AD conversion is rapidly carried out with a low load, and high-quality digital image signals are output by simultaneous AD conversion, without increasing the sizes of a pixel array and an optical system.  
     A pixel array ( 110 ) includes pixels ( 111 ) each including a photoelectric transducer and pixel transistors and outputs analog pixel signals. An AD memory ( 130 ) includes unit memories ( 131 ) in a two-dimensional array corresponding to a pixel arrangement in the pixel array ( 110 ), sequentially stores the analog pixel signals read through vertical signal lines, and carries out various types of processes, for example, AD conversion, fixed-pattern noise removal by CDS, and gain adjustment. AD converter circuits ( 132 ) are provided for the respective unit memories ( 131 ) in the AD memory ( 130 ). The AD converter circuits ( 132 ) convert the analog pixel signals read from the individual pixels to digital pixel signals.

TECHNICAL FIELD

The present invention relates to solid-state imaging apparatuses, forexample, CMOS image sensors that include two-dimensional pixel arraysincluding pixels and that read signals from the pixels in the pixelarrays to process these signals.

BACKGROUND ART

In general, CMOS image sensors are fabricated in a MOS manufacturingprocess. Thus, unlike CCD image sensors, pixel arrays and AD convertercircuits can be mounted on the same chip.

Three on-chip structures are known about AD converter circuits, asdescribed below.

FIG. 6 is a schematic view illustrating a typical structure of a CMOSimage sensor including such on-chip AD converter circuits. In FIG. 6,shaded blocks 200A, 200B, and 200C show three typical layouts of ADconverter circuits. However, in practice, one of these layouts isadopted.

The structure of a known CMOS image sensor will now be described withreference to FIG. 6.

As shown in the drawing, this CMOS image sensor includes a pixel array210, a vertical (V) selection circuit 220, column-signal processingunits 230, a horizontal (H) selection circuit 240, and an output unit250 on one chip.

The pixel array 210 includes many pixels in a two-dimensional array (amatrix).

The V selection circuit 220 sequentially selects the pixels in the pixelarray 210 row by row in the vertical direction (the direction alongcolumns) to drive the selected pixels.

The column-signal processing units 230 correspond to respective columnsof the pixels in the pixel array 210 and sequentially receive signalsfrom the individual pixels 211 to, for example, remove fixed-patternnoise and adjust gain.

The H selection circuit 240 sequentially selects the column-signalprocessing units 230 in the direction along rows to output theindividual pixel signals processed in the column-signal processing units230 to an output line 241.

The output unit 250 receives the pixel signals from the output line 241and finally processes these signals to output the processed signals asimage signals.

In such a CMOS image sensor, the following three types of structuresincluding on-chip AD converter circuits are possible.

The shaded blocks 200A in FIG. 6 show a typical layout disclosed in, forexample, U.S. Pat. No. 5,461,425. In this layout, one AD convertercircuit is provided for each pixel 211 to carry out AD conversion foreach pixel and to output a digitized pixel signal from the pixel 211(hereinafter, referred to as pixel-level AD conversion).

The shaded blocks 200B in FIG. 6 show another typical layout disclosedin, for example, Japanese Patent No. 253234. In this layout, one ADconverter circuit is provided for each of the column-signal processingunits 230 to carry out AD conversion for each column and to output adigitized pixel signal from the column-signal processing unit 230(hereinafter, referred to as column-level AD conversion).

The shaded blocks 200C in FIG. 6 show another typical layout. In thislayout, one AD converter circuit is provided for the output unit 250 tocarry out sequential AD conversion on the signals from the output line241 and to output a digitized pixel signal from the output unit 250 tothe exterior of the chip (hereinafter, referred to as chip-level ADconversion). This layout is equivalent to that of an AD convertercircuit connected to a device outputting analog signals.

The three types of AD conversion described above have the followingproblems.

(1) The pixel-level AD conversion can be simultaneously carried out forall the pixels, thereby enabling high-speed processing. However, sinceone AD converter circuit is provided in each pixel, the size of thepixel is increased. As a result, the area of the pixel array and thesize of an optical system are disadvantageously increased. On the otherhand, the aperture ratio (the area ratio of a photodiode to a pixel) isdecreased, so that the sensitivity is disadvantageously decreased.

(2) The pixels used in the column-level AD conversion have a simplerstructure than those in the pixel-level AD conversion. Thus, the size ofthe pixels can be reduced. However, when one image frame is output, ADconversion must be carried out as many times as the number of rows (forexample, several hundred to several thousand times), and thus the speedof the column-level AD conversion is disadvantageously low.

Moreover, since this AD conversion is carried out in a short time, thebandwidth of the circuit needs to be increased. Thus, the noise becomeslarge.

Moreover, since AD conversion of one frame is sequentially carried outrow by row, the difference between the timing of AD conversion of thefirst row and that of the last row is one frame period. Thus, this ADconversion is not suitable when time shifting in a screen needs to beminimized (for example, when an image of an object that moves quickly iscaptured).

(3) The characteristics of the chip-level AD conversion are the same asthose of the column-level AD conversion. That is, the pixels have asimple structure. However, when one image frame is output, AD conversionmust be carried out as many times as the number of pixels (for example,several hundreds of thousand to several million times), and thus thespeed of the chip-level AD conversion is even lower than that of thecolumn-level AD conversion.

Moreover, since this AD conversion is carried out in a short time, thebandwidth of the circuit needs to be increased. Thus, the noise is evenlarger than that in the column-level AD conversion. Moreover, since ADconversion of pixel signals for one frame is sequentially carried outpixel by pixel, the difference between the timing of AD conversion ofthe first pixel and that of the last pixel is one frame period. Thus,this AD conversion is not suitable when time shifting in a screen needsto be minimized.

It is an object of the present invention to provide a solid-stateimaging apparatus that can rapidly carry out AD conversion with a lowload and that can output high-quality digital image signals bysimultaneous AD conversion, without increasing the sizes of a pixelarray and an optical system.

DISCLOSURE OF INVENTION

To achieve the object, a solid-state imaging apparatus according to thepresent invention includes a pixel array that includes a plurality ofpixels in a two-dimensional array; an AD memory that includes aplurality of unit memories in a two-dimensional array corresponding to apixel arrangement in the pixel array, each unit memory including an ADconverter circuit; a pixel-array scanning circuit that scans the pixelarray to read analog signals from the individual pixels to the ADmemory; and a memory scanning circuit that scans the AD memory to outputdigital signals from the individual unit memories.

The solid-state imaging apparatus according to the present inventionincludes the AD converter circuits in the respective unit memories inthe AD memory that corresponds to the two-dimensional pixel array, andcarries out AD conversion on signals read from the individual pixelsusing the AD memory.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic view illustrating the structure of a CMOS imagesensor according to an embodiment of the present invention includingon-chip AD converter circuits.

FIG. 2 is a schematic view illustrating AD converter circuits in anotherembodiment.

FIG. 3 is a circuit diagram illustrating typical circuits in one unitmemory in an AD memory shown in FIG. 1.

FIG. 4 is a timing chart illustrating a typical operation of the ADmemory shown in FIG. 1.

FIG. 5 is a schematic view illustrating a camera-module-type solid-stateimaging apparatus according to another embodiment of the presentinvention.

FIG. 6 is a schematic view illustrating a typical structure of a knownCMOS image sensor including on-chip AD converter circuits.

BEST MODE FOR CARRYING OUT THE INVENTION

A solid-state imaging apparatus according to an embodiment of thepresent invention will now be described.

FIG. 1 is a schematic view illustrating the structure of a CMOS imagesensor according to the embodiment of the present invention includingon-chip AD converter circuits.

As shown in the drawing, this CMOS image sensor includes a pixel array110, a V selection circuit 120, an AD memory (memory block) 130, amemory V selection circuit 140, an H selection circuit 150, and anoutput unit 160 on one chip.

The pixel array 110 includes many pixels 111 in a two-dimensional array(a matrix) and outputs analog pixel signals detected by the individualpixels through output signal lines (vertical signal lines) provided forindividual pixel columns.

Each pixel 111 may have any type of circuit structure. For example, thepixel 111 includes a photoelectric transducer (for example, aphotodiode), a transfer transistor that transfers signal chargegenerated at the photoelectric transducer to a floating diffusion (FD)part, an amplifying transistor that converts potential change due to thesignal charge transferred to the FD part to an electrical signal andthat outputs this electrical signal, a selecting transistor thatconnects the output of the amplifying transistor to the output signallines (vertical signal lines), and a reset transistor that resets thepotential in the FD part.

The V selection circuit 120 sequentially selects the pixels in the pixelarray 110 row by row in the vertical direction (the direction alongcolumns) to drive the selected pixels. The V selection circuit 120constitutes a pixel-array scanning circuit.

The AD memory 130 includes unit memories 131 in a two-dimensional array.The unit memories 131 correspond to the pixels in the pixel array 110.The AD memory 130 sequentially stores the analog pixel signals readthrough the vertical signal lines to carry out various types ofprocesses, for example, AD conversion, fixed-pattern noise removal byCDS, and gain adjustment. The unit memories 131 are composed of DRAMs.

AD converter circuits 132 are provided for the respective unit memories131 in the AD memory 130 to convert the analog pixel signal read fromthe individual pixels to digital pixel signals.

In the structure shown in FIG. 1, the pixels 111 in the pixel array 110correspond to the unit memories 131 in the AD memory 130 in a one-to-onerelationship. Alternatively, a plurality of pixels may correspond to oneunit memory in an N-to-one relationship (N≧2). In this arrangement, oneunit memory sequentially processes a plurality (N) of pixels. When theunit memories 131 are disposed in an array having as many columns as thepixel array 110 and at least two rows, simultaneous AD conversion ofsignals from all the pixels in one screen can be carried out. Thus, thetime required for the AD conversion is less than those in the knownimaging apparatuses described above.

For example, when the AD memory includes half as many rows as the pixelarray as shown in FIG. 2, simultaneous AD conversion is alternatelycarried out on signals from one half of all the pixels. Thereby, thetime required for AD conversion of signals from all the pixels in ascreen can be reduced.

When signals are read at an accelerated rate to carry out high-speedimage capturing at a low resolution, the time required for AD conversionof signals of one frame can be drastically reduced, thereby facilitatinghigh-speed image capturing. In the solid-state imaging apparatus shownin FIG. 2, for example, when signals from pixels in two sequential rowsare combined to be read, the AD memory can carry out simultaneous ADconversion of signals from pixels in one frame. Moreover, for example,when the number of rows to be combined is increased or when the numberof rows included in the AD memory having the structure other than thatshown in FIG. 2 is less than one half of that in the pixel array and isat least two, AD conversion can be carried out in the same manner.

In this embodiment, the unit memories in the AD memory 130 are in anarray so as to correspond to one image frame, and AD conversion iscarried out for one frame. Thus, this AD conversion is referred to asframe-memory level AD conversion.

The memory V selection circuit 140 scans and drives the individual unitmemories 131 in the AD memory 130 to output digital pixel signalsprocessed in the individual unit memories 131.

The H selection circuit 150 sequentially selects the AD memory 130 inthe direction along rows to output the digital pixel signals processedin the AD memory 130 to an output line 151. The memory V selectioncircuit 140 and the H selection circuit 150 constitute a memory-scanningcircuit.

The output unit 160 receives the digital pixel signals from the outputline 151 and finally processes these signals to output the processedsignals to the exterior of the chip as digital image signals.

In the frame-memory level AD conversion according to this embodiment,the pixel signals from the pixel array 110 can be transferred to the ADmemory 130 in a short time, and simultaneous AD conversion can be thencarried out on signals from all the pixels. Thus, unlike knownpixel-level AD conversion, the size of each pixel is not increasedbecause the pixel has no AD converter circuit, or the aperture ratio isnot decreased. Furthermore, unlike the column-level AD conversion andthe chip-level AD conversion, only a single AD conversion is requiredfor one frame, thereby enabling high-speed processing. Moreover, each ADconversion can be carried out at a low rate. Thus, the bandwidth of theAD converter circuit can be decreased to reduce the noise.

FIG. 3 is a circuit diagram illustrating typical circuits in one unitmemory 131 in the AD memory 130 according to this embodiment. FIG. 4 isa timing chart illustrating a typical operation in the AD memory 130according to this embodiment.

The structure of one unit memory 131 will now be described withreference to FIG. 3.

The unit memory 131 includes a correlated double sampling (CDS) circuit170 that detects the difference between a reset-level voltage and asignal-level voltage from each pixel through one vertical signal line133 and that removes fixed-pattern noise generated in the pixel. Theunit memory 131 further includes an AD converter circuit 180 (that is,corresponding to the AD converter circuits 132 shown in FIG. 1) thatcompares the differential signal generated in the CDS circuit 170 with aramp pulse to output a digital signal value. In this embodiment, thepixel circuit outputs the reset-level voltage corresponding to azero-level voltage and the signal-level voltage less than thereset-level voltage.

As shown in FIG. 3, the CDS circuit 170 includes switches (SW1 and SW2)171 and 172, capacitors (C1 and C2) 173 and 174, and a differentialamplifier 175.

The AD converter circuit 180 in the illustration has a 10-bit datawidth. Each bit includes a converting transistor (Tr0 to Tr9) 181, asampling capacitor 182, and an outputting transistor 183.

The operation of the AD memory 130 will now be described with referenceto FIG. 4. In waveform charts in FIG. 4, a ramp voltage is analog and isshown in a different scale from other scales used for other signals.

(1) Period for reading signals from the pixel array 110 to the AD memory(memory block) 130 [T1]

Signals are read from the pixel array 110 row by row and are written tothe unit memories 131 in the AD memory 130. The unit memories 131correspond to the respective pixels.

The operation for each row is as follows:

(1-1) First, the switches 171 and 172 are turned on while thereset-level voltage is output from each pixel 111 through the verticalsignal line 133.

The potential of the capacitor 173 at a portion close to the switch 171is set to the reset level. On the other hand, at the place on theopposite side of the capacitor 173 from this portion, a ramp voltage isapplied to the positive (+) input terminal of the differential amplifier175 through a ramp-signal supply line (ramp wiring line) 191. Thus, whenthe switch 172 is turned on, the voltage across the negative (−) inputterminal and the output terminal of the differential amplifier 175 isclamped to the ramp voltage.

(1-2) Then, the switch 172 is turned off, and the signal-level voltageis output from each pixel through the vertical signal line 133. At thistime, the potential at the negative (−) input terminal of thedifferential amplifier 175 changes through the capacitor 173 in thenegative direction in proportion to the difference between thereset-level voltage and the signal-level voltage. That is, a signalvoltage free from fixed-pattern noise in the pixel is input to thenegative (−) input terminal.

As a result, the output of the differential amplifier 175 increases tothe “High” level, and the transistor 181 is turned on.

(1-3) When the switch 171 is turned off at this timing, the verticalsignal line 133 is disconnected from the circuits, and this status ismaintained.

During this period, the ramp signal is at the “High” level. Voltages atboth a clock wiring line (ck wiring line) 192 for driving the transistor181 and a clock wiring line (word wiring line) 193 for driving thetransistor 183 are at the “Low” level.

The operation described above will be repeated for all rows to readsignals of one frame into the AD memory.

(2) AD Conversion period [T2]

Next, clocks ck[0] to ck[9] for driving the transistors 181 count upusing 10 bits while the ramp voltage is changed from the “High” level tothe “Low” level. When the ramp voltage falls below the voltage at thenegative (−) input terminal of the differential amplifier 175 that ismaintained in period (1), the output of the differential amplifier 175is inverted, and values (“High”/“Low”) of the clocks ck[0] to ck[9],that is, the results of AD conversion using 10 bits, at this time arestored in the respective capacitors 182.

In this embodiment, since the ramp voltage and the clocks ck[0] to ck[9]are common across the AD memory, AD conversion is simultaneously carriedout on all signals of one frame. The capacitors 182 each store a value“High” or “Low”, and thus function as a DRAM.

(3) Memory access period [T3]

Next, the word wiring lines 193 for the transistors 183 are driven toread signals from intended pixels in the AD memory through bit wiringlines 194 serving as data output lines. The circuits and the method forreading signals may be the same as those of a regular DRAM. Signals maybe sequentially read from the AD memory row by row, may be read from aportion of the AD memory, or may be read from the AD memory at random.

To read data of the next frame, the operation described above, startingfrom the read operation in period (1), is similarly carried out. Theread operation in period (1) is carried out row by row. Thus, evenduring this period for reading signals from the pixel array to the ADmemory, rows that are not currently subjected to the reading operationin the AD memory can be accessed. The operation described above will berepeated.

In the known CMOS image sensor including no frame memory, even whensignals of one row are simultaneously read to the column-signalprocessing units, the column-signal processing units of respectivecolumns are sequentially selected to output the signals to a horizontalsignal line. The time required for the signal-outputting operation ofone row is several to several ten times that for the signal-readingoperation of one row. The next row cannot be read until this sequentialprocess completes.

In contrast, according to the method of this embodiment, one readingcycle for one row completes at the completion of reading signals of onerow to the AD memory 130. Thus, the time required for one reading cyclefor one row is several tenths to several hundredths of that in a knownCMOS image sensor. This means that the time difference in reading rowsis decreased. Thus, time shifting in a screen can be reduced by a factorof several to several tens. When an image of a moving object iscaptured, this time shifting causes deformation in an image of theobject. According to the method of this embodiment, the deformation canbe reduced by a factor of several to several tens. In this embodiment,since signals are read from the pixels in a method used in the knownCMOS image sensor, a known method for suppressing deformation in animage by exposure-time synchronization can be applied to thisembodiment, as in the known CMOS image sensor.

Moreover, according to the method of this embodiment, AD conversion issimultaneously carried out on all signals of one frame, and thus iscompleted in a short time.

Moreover, since frame memories are accessed when signals are read fromthe AD memory 130, the read operation need not be carried out in rowsequence, but can be carried out in any sequence. Moreover, othersignals from the exterior of the AD memory 130 can be written to the ADmemory 130 through the word lines and the bit lines, as in a regularDRAM.

Moreover, electronic shuttering can be carried out by resetting thepixels at a predetermined timing before signals are read from thepixels, as in the known CMOS image sensor.

In the embodiment described above, the pixel circuit outputs thereset-level voltage (a voltage corresponding to signal zero) and thesignal-level voltage less than the reset-level voltage. Alternatively,other types of pixel circuit may be used.

Moreover, the AD memory may have structures other than that describedabove. For example, one AD converter circuit may be assigned to aplurality of pixels.

Moreover, the AD converter circuit may be a chopper-type comparator or adelta-sigma (ΔΣ) type AD converter. Moreover, for example, SRAM-typememories may be used instead of the DRAM-type.

The solid-state imaging apparatus according to the present invention mayinclude elements other than those described above. For example, acamera-module-type solid-state imaging apparatus 303 includes an opticalsystem 300, an imaging unit 301, and a signal-processing chip 302, asshown in FIG. 5.

Moreover, the rows and the columns in the two-dimensional arrangement inthe pixel array and the AD memory are not substantially distinct fromeach other. At least, the pixels and the unit memories are disposed intwo directions intersecting at an angle close to a right angle. In thisarrangement, depending on the way of viewing the solid-state imagingapparatus, pixel rows can be viewed as pixel columns and vice versa, andunit-memory rows can be viewed as unit-memory columns and vice versa.

INDUSTRIAL APPLICABILITY

As described above, in the solid-state imaging apparatus according tothe present invention, the AD converter circuits are provided for therespective unit memories in the AD memory that corresponds to thetwo-dimensional pixel array. Since these AD converter circuits carry outAD conversion on signals read from the respective pixels, AD conversioncan be carried out as distributed processing among the AD convertercircuits disposed in an array. Thus, the total rate of this ADconversion is higher than those of the column-level AD conversion andthe chip-level AD conversion described above. Moreover, the bandwidth ofeach AD converter circuit can be reduced to obtain signals that aresubstantially free from the noise.

Moreover, since the AD converter circuit is not provided in each pixel,the structure of the pixel circuit can be simplified, and the apertureratio of the pixel can be increased to increase the sensitivity of thepixel array. Moreover, since pixel signal can be read from the pixelarray to the AD memory in a short time, time shifting in processing ascreen can be reduced. Thus, even when an image of a moving object iscaptured, a high-quality image that is substantially free fromdeformation can be achieved.

Moreover, since the frame memories are accessed when signals are readfrom the AD memory, the read operation need not be carried out in rowsequence, but can be carried out in any sequence. Moreover, othersignals from the exterior of the AD memory can be written to the ADmemory through the word lines and the bit lines, as in a regular DRAM.

1. A solid-state imaging apparatus comprising: a pixel array that includes a plurality of pixels in a two-dimensional array; an AD memory that includes a plurality of unit memories in a two-dimensional array corresponding to a pixel arrangement in the pixel array, each unit memory including an AD converter circuit, a pixel-array scanning circuit that scans the pixel array to read analog signals from the individual pixels to the AD memory; and a memory scanning circuit that scans the AD memory to output digital signals from the individual unit memories.
 2. The solid-state imaging apparatus according to claim 1, further comprising an output unit that processes the digital signals output from the AD memory and outputs the processed signals to the exterior of the apparatus.
 3. The solid-state imaging apparatus according to claim 1, wherein the individual pixels in the pixel array correspond to the individual unit memories in the AD memory in a one-to-one relationship.
 4. The solid-state imaging apparatus according to claim 1, wherein the individual pixels in the pixel array correspond to the individual unit memories in the AD memory in an N-to-one relationship wherein N≧2.
 5. The solid-state imaging apparatus according to claim 1, wherein the pixel-array scanning circuit reads the signals from the pixel array to the AD memory, the AD memory then carries out AD conversion on the signals, and the memory scanning circuit then outputs the signals from the AD memory.
 6. The solid-state imaging apparatus according to claim 1, wherein AD conversion is simultaneously carried out for all the unit memories in the AD memory.
 7. The solid-state imaging apparatus according to claim 1, wherein the signals are read from the pixel array to the AD memory pixel row by pixel row, and AD conversion is simultaneously carried out for all the unit memories in the AD memory.
 8. The solid-state imaging apparatus according to claim 1, wherein the unit memories comprise DRAMs.
 9. A solid-state imaging apparatus comprising: a pixel array that includes a plurality of pixels in a two-dimensional array; and an AD memory that stores signals read from the pixel array and carries out AD conversion on these signals, the AD memory including a plurality of unit memories at least in a two-dimensional array, and the plurality of unit memories simultaneously carrying out AD conversion on signals from at least two rows of pixels.
 10. The solid-state imaging apparatus according to claim 9, wherein the plurality of unit memories simultaneously carry out AD conversion on signals that are obtained by combining signals read from the pixel array.
 11. The solid-state imaging apparatus according to claim 9, wherein the unit memories carry out noise removal and AD conversion on the signals from the pixel array. 